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CS5156H CPU 5-Bit Nonsynchronous Buck Controller
The CS5156H is a 5-bit nonsynchronous N-Channel buck controller. It is designed to provide unprecedented transient response for today's demanding high-density, high-speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5156H is designed to operate over a 4.25-20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5156H is specifically designed to power Pentium II processors and other high performance core logic. It includes the following features: on board, 5-bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5156H is backwards compatible with the 4-bit CS5151, allowing the mother board designer the capability of using either the CS5151 or the CS5156H with no change in layout. The CS5156H is available in 16 pin surface mount packages.
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16 1 SOIC-16 D SUFFIX CASE 751B CS5156H AWLYWW 1 16
* * * * * * * * * * * * * * * *
Features N-Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5-Bit DAC Backward Compatible with 4-Bit CS5150H/CS5151H 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor Adaptive Voltage Positioning V2 Control Topology Current Sharing Overvoltage Protection
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
1 VID0 VID1 VID2 VID3 SS VID4 COFF VFFB 16 VFB COMP LGND VCC1 NC PGND VGATE VCC2
ORDERING INFORMATION
Device CS5156HGD16 CS5156HGDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2001
1
January, 2001 - Rev. 2
Publication Order Number: CS5156H/D
CS5156H
12 V 5.0 V
0.1 F VCC1 VID0 VID1 VID2 VID3 VID4 330 pF VID0 VID1 VID2 VID3 VID4 COFF SS 0.1 F COMP MBR1535CT 2 1,3 VCC2 VGATE 2.0 H 1.3 V to 3.5 V @ 13 A IRL3103 1200 F/16 V x 3 AIEI
CS5156H
PGND
VFB 3.3 k LGND VFFB 100 pF
0.33 F
1200 F/16 V x 5 AIEI
Figure 1. Application Diagram, Switching Power Supply for Core Logic - Pentium) II Processor
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Lead Temperature Soldering: Storage Temperature Range, TS ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) Value 0 to 150 230 peak -65 to +150 2.0 Unit C C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name VCC1 VCC2 SS COMP VFB COFF VFFB VID0 - VID4 VGATE LGND PGND Max Operating Voltage 16 V/-0.3 V 20 V/-0.3 V 6.0 V/-0.3 V 6.0 V/-0.3 V 6.0 V/-0.3 V 6.0 V/-0.3 V 6.0 V/-0.3 V 6.0 V/-0.3 V 20 V/-0.3 V 0V 0V Max Current 25 mA DC/1.5 A peak 20 mA DC/1.5 A peak -100 A 200 A -0.2 A -0.2 A -0.2 A -50 A 100 mA DC/1.5 A peak 25 mA 100 mA DC/1.5 A peak
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ELECTRICAL CHARACTERISTICS (0C < TA < +70C; 0C < TJ < +125C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V;
DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 F, unless otherwise specified.) Characteristic Error Amplifier VFB Bias Current Open Loop Gain Unity Gain Bandwidth COMP SINK Current COMP SOURCE Current COMP CLAMP Current COMP High Voltage COMP Low Voltage PSRR VCC1 Monitor Start Threshold Stop Threshold Hysteresis VGATE Out SOURCE Sat at 100 mA Out SINK Sat at 100 mA Out Rise Time Out Fall Time Shoot-Through Current VGATE Resistance VGATE Schottky Soft Start (SS) Charge Time Pulse Period Duty Cycle COMP Clamp Voltage VFFB SS Fault Disable High Threshold PWM Comparator Transient Response VFFB Bias Current VFFB = 0 to 5.0 V to VGATE = 9.0 V to 1.0 V; VCC1 = VCC2 = 12 V VFFB = 0 V - - 100 0.3 125 - ns A - - (Charge Time /Pulse Period) x 100 VFB = 0 V; VSS = 0 VGATE = Low - 1.6 25 1.0 0.50 0.9 - 3.3 100 3.3 0.95 1.0 2.5 5.0 200 6.0 1.10 1.1 3.0 ms ms % V V V Measure VCC2 - VGATE Measure VGATE - VPGND 1.0 V < VGATE < 9.0 V; VCC1 = VCC2 = 12 V 9.0 V > VGATE > 1.0 V; VCC1 = VCC2 = 12 V Note 2. Resistor to LGND. Note 2. LGND to VGATE @ 10 mA - - - - - 20 - 1.2 1.0 30 30 - 50 600 2.0 1.5 50 50 50 100 800 V V ns ns mA k mV Output switching Output not switching Start-Stop 3.75 3.70 - 3.90 3.85 50 4.05 4.00 - V V mV VFB = 0 V 1.25 V < VCOMP < 4.0 V; Note 2. Note 2. VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V VCOMP = 0 V; VFB = 2.7 V VFB = 2.7 V; VSS = 5.0 V VFB = 3.0 V 8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2. - 50 500 0.4 30 0.4 4.0 - 60 0.3 60 3000 2.5 50 1.0 4.3 160 85 1.0 - - 8.0 80 1.6 5.0 600 - A dB kHz mA A mA V mV dB Test Conditions Min Typ Max Unit
2. Guaranteed by design, not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued) (0C < TA < +70C; 0C < TJ < +125C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 F, unless otherwise specified.)
Characteristic DAC Input Threshold Input Pull Up Resistance Pull Up Voltage Accuracy (all codes except 11111) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1.3266 1.3761 1.4256 1.4751 1.5246 1.5741 1.6236 1.6731 1.7226 1.7721 1.8216 1.8711 1.9206 1.9701 2.0196 2.0691 1.2191 2.1186 2.2176 2.3166 2.4156 2.5146 2.6136 2.7126 2.8116 2.9106 3.0096 3.1086 3.2076 3.3066 3.4056 3.5046 1.3400 1.3900 1.4400 1.4900 1.5400 1.5900 1.6400 1.6900 1.7400 1.7900 1.8400 1.8900 1.9400 1.9900 2.0400 2.0900 1.2440 2.1400 2.2400 2.3400 2.4400 2.5400 2.6400 2.7400 2.8400 2.9400 3.0400 3.1400 3.2400 3.3400 3.4400 3.5400 1.3534 1.4039 1.4544 1.5049 1.5554 1.6059 1.6564 1.7069 1.7574 1.8079 1.8584 1.9089 1.9594 2.0099 2.0604 2.1109 1.2689 2.1614 2.2624 2.3634 2.4644 2.5654 2.6664 2.7674 2.8684 2.9694 3.0704 3.1714 3.2724 3.3734 3.4744 3.5754 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VID0, VID1, VID2, VID3, VID4 VID0, VID1, VID2, VID3, VID4 - Measure VFB = COMP, 25C TJ 125C 1.00 25 4.85 - 1.25 50 5.00 - 2.40 100 5.15 1.0 V k V % Test Conditions Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS (continued) (0C < TA < +70C; 0C < TJ < +125C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 F, unless otherwise specified.)
Characteristic Supply Current ICC1 ICC2 Operating ICC1 Operating ICC2 COFF Normal Charge Time Extension Charge Time Discharge Current Time Out Timer Time Out Time Fault Mode Duty Cycle VFB = VCOMP; VFFB = 2.0 V; Record VGATE Pulse High Duration VFFB = 0V 10 35 30 50 65 70 s % VFFB = 1.5 V; VSS = 5.0 V VSS = VFFB = 0 COFF to 5.0 V; VFB > 1.0 V 1.0 5.0 5.0 1.6 8.0 - 2.2 11.0 - s s mA No Switching No Switching VFB = COMP = VFFB VFB = COMP = VFFB - - - - 8.5 1.6 8.0 2.0 13.5 3.0 13 5.0 mA mA mA mA Test Conditions Min Typ Max Unit
PACKAGE PIN DESCRIPTION
PACKAGE PIN # SO-16 1, 2, 3, 4, 6 PIN SYMBOL VID0-VID4 FUNCTION Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left open. VID4 selects the DAC range. When VID4 is High (logic one), the DAC range is 2.14 V to 3.54 V with 100 mV increments. When VID4 is Low (logic zero), the DAC range is 1.34 V to 2.09 V with 50 mV increments. VID0 - VID4 select the desired DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage of 1.244 V, allowing for adjustable output voltage, using a traditional resistor divider. Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 A current source provides Soft Start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly discharged by internal 2.0 A current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted. A capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. Fast feedback connection to the PWM comparator. This pin is connected to the regulator output. The inner feedback loop terminates on time. Boosted power for the gate driver. MOSFET driver pin capable of 1.5 A peak switching current. High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the anode of the Schottky diode should be tied to this pin. No connection. Input power for the IC. Signal ground for the IC. All control circuits are referenced to this pin. Error amplifier compensation pin. A capacitor to ground should be provided externally to compensate the amplifier. Error amplifier DC feedback input. This is the master voltage feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace.
5
SS
7 8 9 10 11
COFF VFFB VCC2 VGATE PGND
12 13 14 15 16
NC VCC1 LGND COMP VFB
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VCC2 VCC1 - + 3.90 V 3.85V 60 A 0.7 V SS 2.0 A VID0 VID1 VID2 VID3 VID4 Slow Feedback 5 BIT DAC Error Amplifier + - PWM Comparator - + Maximum On-Time Timeout Normal Off-Time Timeout Extended Off-Time Timeout VFFB Low Comparator R S Q Q PMW Latch Off-Time Timeout GATE = ON GATE = OFF COFF One Shot R S Q COFF 2.5 V + - SS High Comparator VCC1 Monitor Comparator 5.0 V - + Q S FAULT Latch SS Low Comparator R Q VGATE FAULT FAULT PGND
VFB COMP
VFFB
Fast Feedback
- +
LGND
1.0 V
PWM COMP
Time-Out Timer (30 s)
Edge Triggered
Figure 2. Block Diagram
APPLICATIONS INFORMATION THEORY OF OPERATION
V2 Control Method
+
PWM Comparator C
-
The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current.
VGATE
Ramp Signal
VFFB
Output Voltage Feedback VFB
Error Amplifier COMP Error Signal E
- +
Reference Voltage
Figure 3. V2 Control Diagram
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The V2 control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.
Constant Off Time
Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30 s timer, minimizing stress to the power components.
Programmable Output
The CS5156H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5156H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5156H is specifically designed to be backwards compatible with the CS5151H, which uses a four bit DAC code.
Start Up
To maximize transient response, the CS5156H uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time.
Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE output is activated, and the Soft Start capacitor begins charging. The GATE output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE pin drives low for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. Then, the GATE pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by
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the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5).
M 10.0 s M 250 s
Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 2- Inductor Switching Node (2.0 V/div.) Trace 3- 12 V Input (VCC1 and VCC2) (5.0 V/div.) Trace 4- 5.0 V Input (1.0 V/div.) Trace 1- Regulator Output Voltage (5.0 V/div.) Trace 2- Inductor Switching Node (5.0 V/div.)
Figure 6. CS5156H Demonstration Board Enable Startup Waveforms Normal Operation
Figure 4. CS5156H Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output.
During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working into the ESR of the output capacitors (see Figures 7 and 8).
M 2.50 ms
Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 3- COMP PIn (error amplifier output) (1.0 V/div.) Trace 4- Soft Start Pin (2.0 V/div.)
Figure 5. CS5156H Demonstration Board Startup Waveforms
M 1.00 s
Trace 1- Regulator Output Voltage (10 mV/div.) Trace 2- Inductor Switching Node (5.0 V/div.)
If the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see Figure 6).
Figure 7. Peak-to-Peak Ripple on VOUT = 2.8 V, IOUT = 0.5 A (Light Load)
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level, the output capacitor is pre-positioned -40 mV (see Figures 9, 10, and 11). For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor.
M 1.00 s
Trace 1- Regulator Output Voltage (10 mV/div.) Trace 2- Inductor Switching Node (5.0 V/div.)
Figure 8. Peak-to-Peak Ripple on VOUT = 2.8 V, IOUT = 13 A (Heavy Load) Transient Response
The CS5156H V2 control loop's 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called "adaptive voltage positioning". This technique pre-positions the output capacitor's voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifier's reference voltage to be targeted +40 mV high without compromising DC accuracy. A "droop resistor", implemented through a PC board trace, connects the error amplifier's feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the error amplifier's, including the +40 mV offset. When the full load current is delivered, an 80 mV drop is developed across this resistor. This results in output voltage being offset -40 mV low. The result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre-positioned +40 mV. Conversely, when load current suddenly decreases from its maximum
Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 2- Regulator Output Voltage (20 V/div.)
Figure 9. CS5156H Demonstration Board Response to a 0.5 to 13 A Load Pulse (Output Set for 2.8 V)
Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 2- Inductor Switching Node (5.0 V/div.) Trace 3- Output Current (0.5 to 13 Amps) (20 V/div.)
Figure 10. CS5156H Demonstration Board Response to 13 A Load Turn On (Output Set for 2.8 V). Upon Completing a Normal Off Time, The V2 Control Loop Immediately Connects the Inductor to the Input Voltage, Providing 100% Duty Cycle. Regulation is Achieved in Less Than 20 ms
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traces than occurs with constant current limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.
Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 2- Inductor Switching Node (5.0 V/div.) Trace 3- Output Current (13 to 0,5 Amps) (20 mV/div.)
Figure 11. CS5156H Demonstration Board Response to 13 A Load Turn Off (Output Set for 2.8 V). V2 Control Topology Immediately Connects Inductor to Ground, Providing 0% Duty Cycle. Regulation is Achieved in Less Than 10 ms
M 25.0 ms
Trace 4- 5.0 V Supply Voltage (2.0 V/div.) Trace 3- Soft Start Timing Capacitor (1.0 V/div.) Trace 2- Inductor Switching Node (2.0 V/div.)
PROTECTION AND MONITORING FEATURES
VCC1 Monitor
Figure 12. CS5156H Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge
To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75 V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70 V minimum shutdown threshold.
Short Circuit Protection
A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT latch. This causes the MOSFET to shut off, disconnecting the regulator from it's input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 A current source until it reaches it's lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it's extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 A charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it's upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 A/60 A = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board
M 50.0 s
Trace 4- 5.0 V from PC Power Supply (2.0 V/div.) Trace 2- Inductor Switching Node (2.0 V/div.)
Figure 13. Startup with Regulator Output Shorted Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it's input voltage.
External Output Enable Circuit
On/off control of the regulator can be implemented through the addition of two additional discrete components
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(see Figure 14). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition.
5.0 V
MMUN2111T1 (SOT-23) 5 SS
CS5156H
8V FFB IN4148 Shutdown Input
Trace 4- 5.0 V Input (2.0 V/div.)
M 2.50 ms
Trace 3 - 12 V Input (VCC1) and (VCC2) (10 V/div.) Trace 1- Regulator Output Voltage (1.0 V/div.) Trace 2- Power Good Signal (2.0 V/div.)
Figure 14. Implementing Shutdown with the CS5156H External Power Good Circuit
Figure 16. CS5156H Demonstration Board During Power Up. Power Good Signal is Activated when Output Voltage Reaches 1.70 V. Selecting External Components
An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation:
VPower Good + (R1 ) R2) 0.65 V R2
The CS5156H can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection.
NFET Power Transistors
This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good.
5.0 V R3 10 k VOUT R1 10 k R2 6.2 k PN3904 Power Good
PN3904
CS5156H
Figure 15. Implementing Power Good with the CS5156H
Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and use logic level MOSFETs. A charge pump may be easily implemented to permit use of standard MOSFETs or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. The gate driver output is specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of its bias supply when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;
VGATE + 12 V * 5.0 V + 7.0 V
(see Figure 17.)
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"Droop" Resistor for Adaptive Voltage Positioning
Adaptive voltage positioning is used to reduce output voltage excursions during abrupt changes in load current. Regulator output voltage is offset +40 mV when the regulator is unloaded, and -40 mV at full load. This results in increased margin before encountering minimum and maximum transient voltage limits, allowing use of less capacitance on the regulator output (see Figure 9). To implement adaptive voltage positioning, a "droop" resistor must be connected between the output inductor and output capacitors and load. This is normally implemented by a PC board trace of the following value:
M 1.00 s
Channel 3 = VGATE M1 = VGATE - 5.0 VIN Channel 2- Inductor Switching Node
RDROOP + 80 mV IMAX
Figure 17. CS5156H Gate Drive Waveforms Depicting Rail to Rail Swing
Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non-load current carrying circuit trace.
Input and Output Capacitors
The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs and the Schottky diode may be estimated as follows; Switching MOSFET:
Power + ILOAD2 RDSON duty cycle
Schottky diode:
Power + VFORWARD ILOAD (1 * duty cycle)
These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required.
Output Inductor
Duty Cycle =
VOUT ) VFORWARD VIN ) VFORWARD * (ILOAD RDSON OF SYNCH FET)
The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. THERMAL MANAGEMENT
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF + COFF 4848.5
Thermal Considerations for Power MOSFETs and Diodes
When the VFFB pin is less than 1.0 V, the current charging the COFF capacitor is reduced. The extended off time can be calculated as follows:
TOFF + COFF 24, 242.5
In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows:
Thermal Impedance + TJUNCTION(MAX) * TAMBIENT Power
Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor:
COFF + Perioid (1 * duty cycle) 4848.5
A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components.
where:
Period + 1 switching frequency
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CS5156H
EMI Management
As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions.
RTRACE + 80 mV IMAX
2.0 H
This causes the output voltage to be +40 mV with no load, and -40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET. Route gate drive signals VGATE (pin 10) with a trace that is a minimum of 0.025 inches wide.
VCC 0.1 F 15 1.0 F VCOMP To the negative terminal of the input capacitors 11
33 1000 pF
Figure 18. Filter Components
2.0 H
8 + 1200 pF x 3.0/16 V 5
100 pF VFFB
SOFT START
Figure 19. Input Filter Layout Guidelines
OFF TIME To the negative terminal of the output capacitors
1. Place 12 V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGND). 2. Connect pin 11 (PGND) with a separate trace to the ground terminals of the 5.0 V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it's ground terminal with a separate, wide trace directly to pin 14 (LGND). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGND). 6. To implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (VFB) and 8 (VFFB) to the regulator output right at the inductor terminal. Connect inductor to the output capacitors via a trace with the following resistance:
Figure 20. Layout Guidelines
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CS5156H
5.0V
0.1 F MBRS 120
MBRS120 MBRS120 1.0 F + 100 F/10 V x 3 Tantalum
1.0 F
VCC1 VID0 VID1 VID2 VID3 VID4 COFF
VCC2
VGATE
Si4410DY 3.0 H 3.3 V/10 A
2 MBR1535CT
CS5156H
1,3
330 pF SS 0.1 F COMP LGND 0.33 F
PGND VFB 3.3 k VFFB + 100 pF 100 F/10 V x 3 Tantalum
Figure 21. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter
12 V 1.0 F
3.3 V
+ VCC1 VID0 VID1 VID2 VID3 VID4 COFF 330 pF VFB VCC2 VGATE Si9410
33 F/25 V x 3 Tantalum 5.0 H 2.5 V/7.0 A
CS5156H
MBR1535CT
2 1,3
+
100 F/10 V x 2 Tantalum
SS 0.1 F COMP LGND 0.33 F
PGND 3.3 k VFFB 100 pF
Figure 22. Additional Application Diagram, 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias
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CS5156H
5.0V MBRS 120
0.1 F
MBRS120 1.0 F + 100 F/10 V x 3 Tantalum Remote Sense VCC1 VID0 VID1 VID2 VID3 VID4 COFF VFB 2 10 + MBR1535CT 100 F/10 V x 3 Tantalum VCC2 VGATE Si4410 3.0 H 3.3 V/10 A
MBRS120 1.0 F
CS5156H
1,3
330 pF SS 0.1 F COMP LGND 0.33 F
PGND 3.3 k VFFB 100 pF Connect to other circuits for current sharing
Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing
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CS5156H
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-16 28 115 Unit C/W C/W
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CS5156H
Notes
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CS5156H
Notes
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CS5156H
Notes
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CS5156H
V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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CS5156H/D

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